1. Field of the Invention
The present invention relates to integrated circuit (IC) fabrication processes and techniques. More particularly, the present invention relates to a method and apparatus for capturing and using design intent in an IC fabrication process.
2. Description of the Related Art
Modern integrated circuit (IC) design and fabrication processes are complex and require the input of many entities. Generally design companies prepare integrated circuit designs that are then released to an IC manufacturing facility that uses integrated circuit fabrication equipment in a manner defined by the design release to fabricate the integrated circuit. In many instances the design release, although it captures the specific layout of the integrated circuit, does not capture the design intent of the designer. This is because design intent may encompass a variety of parameters beyond merely the physical layout of circuit elements; for example, design intent can include guidelines drawn to criteria such as circuit yield, speed and power consumption, timing closure, among others. Thus, even if the physical layout of circuit elements appears to translate correctly from design to fabrication, this does not necessarily confirm that the fabricated IC embodies all parameters of the designer's intent. As such, critical aspects of the integrated circuit that were considered by the designer are not tested nor considered as critical by the IC manufacturing facility during IC fabrication. Consequently, the IC may not operate as intended by the designers.
FIG. 1 depicts a block diagram of an IC fabrication process. The process 100 is divided into a circuit design phase 102 and a circuit fabrication phase 104. Equipment 106 is provided to the circuit fabrication phase 104 to facilitate fabrication of the IC. In the circuit design phase 102, the design company 108 utilizes electronic design automation (EDA) tools 110 and component macro modules 112 to design the integrated circuit. The EDA tools rely on technical files 114 and the component macro modules 112 rely on technical files 116. The component macro modules 112 comprise a plurality of macros, where each macro defines a particular type of integrated circuit such as static random access memory, memory management unit (MMU), and other standard logic circuitry. The technical files 114 or 116 that are used to support the design are augmented with circuit and transistor models and model parameters that are supplied by the IC manufacturing facility 122. The models are developed and tested using transformations that ensure that the physical device will theoretically have the desired electrical characteristics. These models are generated using physics derivations and empirical analysis to correlate a measurable, physical feature to a design or performance requirement. One such model type for modeling transistors is a SPICE model. Other models may be used for modeling photolithography, interconnect structures and the like. The facility 122 supplies this information such that macros are developed to be optimized for a particular facility's equipment. As such, the component macros are developed and supplied to the design companies without charge. The macro developers are not paid directly for their component macros, but are paid on a royalty basis as each integrated circuit that uses the macro is produced by the IC manufacturing facility. Alternatively, access fees are charged for the component macros.
The ultimate design release is a layout that utilizes a plurality of component macros and other logic that interconnect the components to form an integrated circuit. The design release is sent to the IC manufacturing facility 122 along path 120.
The IC manufacturing facility 122 comprises EDA tools 124 that use the design release to produce masks for fabricating the integrated circuit and a wafer fabrication center 126 that uses the masks and the equipment supplied by the equipment manufacturer 130 along path 128 to fabricate the integrated circuit. Alternatively, the EDA tools 124 may be used in a separate facility from the IC manufacturing facility. The equipment manufacturer 130 supplies fabrication tools 132, methods 134 of using the tools 132, and various metrology equipment 136 that are used together for fabricating and testing wafers and circuits. The test results can be used to optimize the integrated circuit fabrication process performed by the tools 132.
The IC manufacturing facility 122 uses the equipment supplied on path 128 to fabricate masks and ultimately to fabricate the integrated circuit.
As mentioned above, various transistor models and parasitic capacitance models and model parameters are supplied from the IC manufacturing facility 122 to the circuit design phase 102 as components of the technical files 114, 116. Such feedback of the models and model parameters enables the design company to produce transistor designs that can be fabricated by the IC manufacturing facility 122.
The integrated circuits produced by the IC manufacturing facility should meet the design specifications that the design company was striving to achieve in the design release. However, the IC design assumes the IC dimensions are absolute and invariant, while the physical characteristics of an integrated circuit are generally statistical in nature such that the design company never achieves the exact physical characteristics that had been designed. The statistical nature of the physical characteristics (e.g., the layout) will result in a statistical variation in the electrical characteristics of the integrated circuit. Furthermore, the design company may have had critical characteristics (e.g., critical regions or critical pathways) around which the integrated circuit was designed and the manufacturing facility does not know of, nor consider, these critical characteristics when fabricating the IC. Consequently, the IC manufacturing facility ultimately produces an integrated circuit that is not optimized for these critical characteristics.
Therefore, there is a need in the art to capture and use the design intent of a designer such that the integrated circuit produced by a foundry is optimized using the design intent.